S. Samanta and S. Sarkar,"Mismatch error compensation of hybrid CS-DAC to achieve high figure of merit utilizing on-chip self-healing assisted swap-enabled randomization technique", International Journal of Circuit Theory and Applications, vol.52, no.5, pp.2191-2204, Wiley, May 2024, 10.1002/cta.3875       Article

D. Kumaradasan and S. Sarkar,"A low-power 10-bit SAR ADC with an integrated CDAC and C-MOSCAP DAC for implantable pacemakers", in 28th International Symposium on VLSI Design and Test (VDAT-2024), IEEE VDAT 24 2024       Inproceedings

D. Kumaradasan, S. K. Kar, and S. Sarkar,"An 8-bit 100 kS/s Low Power SAR ADC with Modified EPC for Bio-Medical Applications", in 2023 IEEE Silchar Subsection Conference (SILCON), pp.1-6, IEEE, January 2024, 10.1109/SILCON59133.2023.10404914       Inproceedings

I. Dash, S. K. Kar, and S. Sarkar,"Noise analysis in switched capacitor-based differential capacitive interfacing circuits", in 2024 IEEE 21st India Council International Conference (INDICON), IEEE 2024, 10.1109/INDICON63790.2024.10958540       Inproceedings

I. Dash, R. Maheshwari, S. K. Kar, and S. Sarkar,"A capacitance mismatch cancellation technique for differential capacitive interfacing circuit", in 2024 IEEE 21st India Council International Conference (INDICON), pp.1-5, IEEE 2024, 10.1109/INDICON63790.2024.10958311       Inproceedings

D. Kumaradasan, S. K. Kar, and S. Sarkar,"An 8-bit 1 MS/s low-power SAR ADC with an enhanced EPC for implantable medical devices", in 2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp.9-14, IEEE, July 2024, 10.1109/ISVLSI61997.2024.00014       Inproceedings

D. Kumaradasan, S. K. Kar, and S. Sarkar,"A low-power 10-bit SAR ADC with an integrated CDAC and C-MOSCAP DAC for implantable pacemakers", in 2024 28th International Symposium on VLSI Design and Test (VDAT), pp.1-6, IEEE, September 2024, 10.1109/VDAT63601.2024.10705705       Inproceedings

M. and S. Sarkar,"A 13-bit resolution high performance time domain comparator using intermediate buffer based VCO", in TENCON 2024 - 2024 IEEE Region 10 Conference (TENCON), pp.1545-1548, IEEE, December 2024, 10.1109/TENCON61640.2024.10902767       Inproceedings

K. A. Ahmed, J. H. Te, S. Sarkar, and M. Alioto,"Dual-Mode conversion gating, comparator merging and reference-less calibration for 2.7X Energy reduction in SAR ADCs under low-activity inputs", IEEE Solid-State Circuits Letters, vol.6, IEEE 2023, 10.1109/LSSC.2023.3246063       Article

S. Samanta and S. Sarkar,"A 10-bit CS-DAC using Fully Random Rotation based DEM and Code Independent Output Impedance Compensation", AEU – International Journal of Electronics and Communications, vol.161, pp.154528, AEU 2023, https://doi.org/10.1016/j.aeue.2023.154528       Article