A. Mukherjee and A. S. Dhar,"Triple transistor based fault tolerance for resource constrained applications", Microelectronics Journal, vol.68, pp.1-6, Elsevier, October 2017, 10.1016/j.mejo.2017.08.005       Article

A. Mukherjee and A. S. Dhar,"Choice of granularity for reliable circuit design using dynamic reconfiguration", Microelectronics Reliability, vol.63, pp.291-303, Elsevier, August 2016, 10.1016/j.microrel.2016.04.001       Article

A. Mukherjee and A. S. Dhar,"Real-time fault-tolerance with hot-standby topology for conditional sum adder", Microelectronics Reliability, vol.55, no.3-4, pp.704-712, Elsevier, March 2015, 10.1016/j.microrel.2014.12.011       Article

A. Mukherjee and A. S. Dhar,"Fault tolerant architecture design using quad-gate-transistor redundancy", IET Circuits, Devices & Systems, vol.9, no.3, pp.152-160, IET, May 2015, 10.1049/iet-cds.2014.0106       Article

A. Mukherjee and A. S. Dhar,"Design of a fault-tolerant conditional sum adder", in Progress in VLSI Design and Test16th, vol.7373, pp.217-222, Springer, lecture notes in computer science, Shibpur, India 2012, 10.1007/978-3-642-31494-0_25       Inproceedings

A. Mukherjee and A. S. Dhar,"Design of a self-reconfigurable adder for fault-tolerant VLSI architecture", in 2012 International Symposium on Electronic System Design (ISED), pp.92-96, IEEE, Kolkata, India, December 2012, 10.1109/ISED.2012.21       Inproceedings