Course Details
Subject {L-T-P / C} : CS2074 : Computer Organization Laboratory { 0-0-3 / 2}
Subject Nature : Practical
Coordinator : Dr. Arun Kumar
Syllabus
1. Realization of basic logic gates using any hardware description language such as Verilog, VHDL.
2. Design a 4-to-1 multiplexer (MUX) using Verilog (VHDL ) and verify its output on various input combinations.
3. Design a 2-to-4 decoder using Verilog (VHDL).
4. Draw the truth table of the overflow/underflow detector while adding two fixed point numbers represented in 2’s complement.
5. Design the logic circuit in Verilog (VHDL), Design an SR latch.
6. State the truth table of the full subtractor. Design it in Verilog.
7. Design an 8x1 multiplexer using two 4x1 MUX, and Design 4 bit full adder circuit using four 1-bit full adders.
8. Generate G_i and P_i and S_i while adding two x_i, y_i and a carry C_i: Implement a 4-bit carry look-ahead adder.
9. Implement an 8-bit adder cascading two 4-bit carry look-ahead adders.
10. Using the case statement, design an 8-function ALU that takes 4-bit inputs a, b and 3-bit input signal select, and gives 5-bit output.
It implements the following function.
Select Signal Function
3’b000 out=a
3’b001 out=a+b
3’b010 out=a-b
3’b011 out=a/b
3’b100 out=a%b
3’b101 out=a<<1
3’b110 out= a>>1
3’b111 out=(a>b)
case ({s1,s0})
2’b00: out=xx
2’b01:out=xy
2’b10:out=xz
2’b11:out=zz
default:out=yy
endcase
Design a control unit for the GCD processor.
Course Objectives
- To get exposure with hardware description Language.
- To implement adder circuits using basic gates.
- To understand the converter circuits using basic gates.
- To understand the various circuits for ALU, datapath and control units.
Course Outcomes
Student should able to design and implement new digital circuit, embedded system, etc.
Essential Reading
- SAMIR PALNITKAR, Verilog HDL: A Guide to Digital Design and Synthesis, Prentice Hall
- Nazeih M.Botros, HDL Programming VHDL and Verilog, Dreamtech Press
Supplementary Reading
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