Course Details

Subject {L-T-P / C} : CS4441 : Low Power Systems { 3-0-0 / 3}

Subject Nature : Theory

Coordinator : Prof. Sumanta Pyne

Syllabus

1. Introduction
1.1. The historical background that led to the development of present-day VLSI circuits.
1.2. The importance of low power in high-performance and battery-operated embedded systems.
1.3. Various sources of power dissipation.
1.4. Low-power design methodologies.
2. MOS Fabrication Technology
2.1. The basic metal-oxide–semiconductor (MOS) fabrication processes such as diffusion, photolithography, etc.
2.2. n-type metal–oxide–semiconductor (nMOS) fabrication steps.
2.3. An overview of complementary metal–oxide–semiconductor (CMOS) fabrication steps.
2.4. The latch-up problem. Two approaches to overcome the latch-up problem.
2.5. Short channel effects arising out of smaller dimension of MOS devices are highlighted.
2.6. A brief introduction of emerging MOS technologies such as high-K and Fin field-effect transistor (FinFET) to overcome short channel and other effects.
3. MOS Transistors
3.1. The structure of various types of MOS transistors that can be obtained after fabrication.
3.2. The characteristics MOS transistors with the help of fluid model.
3.3. Three different modes of operation such as accumulation, depletion, and inversion.
3.4. Electrical characteristics of MOS transistors.
3.5. Use of MOS transistors as a switch.
4. MOS Inverters
4.1. Basic characteristics of an inverter and its noise margin
4.2. The advantages and disadvantages of different inverter configurations with their transfer characteristics and noise margin.
4.3. The inverter ratio in different situations. Switching characteristics of MOS inverters.
4.4. Different configurations of MOS inverters on MOS inverters. 4.5. Various delay parameters and their estimation.
4.6. Different circuit configurations such as super buffers, bipolar CMOS (BiCMOS) inverters, and buffer sizing to drive a large capacitive load.
5. MOS Combinational Circuits
5.1. The operation of pass transistor logic circuits.
Advantages and limitations of pass transistor logic circuits. Different members of the pass transistor logic family.
5.2. Logic circuits based on gate logic by considering the realization of NAND and NOR gates. Differences between gate logic and pass transistor logic circuits.
5.3. The operation of MOS dynamic circuits. The charge sharing and charge leakage problems of MOS dynamic circuits. The clock skew problem of MOS dynamic circuits. The operation of the domino-CMOS and NORA-CMOS circuits.
5.4. Realization of several example functions such as full-adder, parity generator and priority encoder using different
logic styles are their comparison.
6. Sources of Power Dissipation
6.1. Various sources of power dissipation in MOS circuits.
The difference between power and energy. Short
circuit power dissipation takes place in CMOS circuits. Derivation of expression for short circuit power dissipation. 6.2. Switching power dissipation in CMOS circuits.
Derivation of expression for switching power dissipation. Calculation of switching activity for different types of
gates and dynamic CMOS circuits. Derivation of expression
for power dissipation due to charge sharing.
6.3. Glitching power dissipation and techniques to reduce it. 6.4. Sources of leakage power dissipation such as subthreshold leakage and gate leakage. Techniques to reduce them. Various mechanisms which affect the subthreshold leakage current.
7. Supply Voltage Scaling for Low Power
7.1. Various voltage scaling techniques starting with static voltage scaling. The challenges involved in supply voltage scaling for low power. The distinction between constant field and constant voltage scaling. The physical level-based approach, device feature size scaling, to overcome the loss in performance. The short-channel effect arising out of feature size scaling.
7.2. Architecture level approaches such as parallelism and pipelining for static voltage scaling. The relevance of multi-core for low power.
7.3. Static voltage scaling exploiting high-level transformation. Multilevel voltage scaling (MVS) approach and various challenges in MVS.
7.4. Dynamic voltage and frequency scheduling (DVFS) approach. 7.5. The adaptive voltage scaling (AVS) approach.
8. Switched Capacitance Minimization
8.1. A system-level approach based on hardware–software co-design.
8.2. Various bus-encoding techniques.
The difference between redundant and non-redundant bus-encoding technique to reduce switching activity. Non-redundant bus encoding technique such as Gray coding technique for address bus. Redundant bus encoding techniques such as one-hot encoding, bus-inversion encoding and T0 encoding techniques.
8.3. Various aspects of clock gating technique to reduce dynamic power dissipation. Clock gating at different levels of granularity is highlighted.
8.4. The basic principle behind gated clock finite state machines (FSMs) to reduce switching activity in FSMs.
8.5. FSM state encoding approach to minimize switching
activity.
8.6. Reducing the switching activity of an FSM using
FSM partitioning.
8.7. The technique of operand isolation to reduce the switching activity of a combinational circuit.
8.8. Pre-computation to reduce switching activity.
8.9. The basic approach of minimizing glitching power.
8.10. Various logic styles including dynamic CMOS and pass transistor logic styles for low-power logic synthesis.
9. Leakage Power Minimization
9.1. Various approaches for the fabrication of multiple threshold voltage transistors.
9.2. Variable threshold voltage CMOS (VTCMOS) approach.
9.3. Transistor stacking approach.
9.4. Run-time leakage power can be minimized by using multiple-threshold voltage (MTCMOS) approach.
9.5. Power-gating technique to minimize leakage power and various issues related to power-gating approaches.
9.6. Power management approach can be used to reduce leakage power dissipation. Its combination with dynamic voltage scaling. 9.7. Isolation strategy.
9.8. State retention strategy.
9.9. Power gating controllers.
9.10. Dual-Vt assignment technique.
9.11. Delay and energy constrained dual-Vt techniques.
9.12. Dynamic Vt scaling.
10. Adiabatic Logic Circuits
10.1. Adiabatic charging. The difference between adiabatic charging and conventional charging of a capacitor.
10.2. Adiabatic amplification.
10.3. The steps of realization of adiabatic logic gates.
10.4. Realization of pulsed power supply. Synchronous and asynchronous pulsed power supplies.
10.5. Stepwise charging and discharging to minimize power
dissipation.
10.6. Various partially adiabatic circuits such as
efficient charge recovery logic (ECRL), positive feedback adiabatic logic (PFAL)and 2N-2N2 and their comparison.
11. Battery-Aware Systems
11.1. Battery gap: ever-increasing power requirement versus the actual rate of growth of energy density of the battery technology.
11.2. An overview of different battery technologies.
11.3. Different characteristics of a rechargeable battery.
11.4. The underlying process of battery discharge.
11.5. Different approaches of battery modeling.
11.6. Realizations of battery-driven systems.
11.7. An example of a battery-aware system.
11.8. Battery-aware sensor networks.
12. Software for Low Power
12.1. Various sources of power dissipation in the computer hardware.
12.2. Machine-independent software optimizations.
12.3. Various loop optimization techniques combined with DVFS. 12.4. Power aware software prefetching.
12.5. Exploitation of the architectural features of the target processor to design energy efficient software.

Course Objectives

Course Outcomes

1. A student can meet the needs of low power and energy efficient design in electronics design automation industry. <br />2. Benefit the research scholars working in the field of low power design. <br />3. Motivate the students from Electrical, Electronics and Computer Engineering to apply the hardware and software techniques covered in this course to various fields of their study.

Essential Reading

Supplementary Reading