Course Details

Subject {L-T-P / C} : CS6123 : Vlsi System Design { 3-0-0 / 3}

Subject Nature : Theory

Coordinator : Prof. Sumanta Pyne

Syllabus

1. Introduction 2 hours
1.1 A Historical Perspective
1.2 Issues in Digiital Integrated Circuit Design
1.3 Quality Metrics of a Digital Design
1.3.1 Cost of an Integrated Circuit
1.3.2 Functionality and Robustness
1.3.3 Performance
1.3.4 Power and Energy Consumption

2. MOS Fabrication Technology 3 hours
2.1 Introduction
2.2 Basic Fabrication Processes
2.2.1 Wafer Fabrication
2.2.2 Oxidation
2.2.3 Mask Generation
2.2.4 Photolithography
2.2.5 Diffusion
2.2.6 Deposition
2.3 nMOS Fabrication Steps
2.4 CMOS Fabrication Steps
2.4.1 The n-Well Process
2.4.2 The p-Well Process
2.4.3 Twin-Tub Process
2.5 Latch-Up Problem and Its Prevention
2.5.1 Use of Guard Rings
2.5.2 Use of Trenches
2.6 Short-Channel Effects
2.6.1 Channel Length Modulation Effect
2.6.2 Drain-Induced Barrier Lowering
2.6.3 Channel Punch Through
2.7 Emerging Technologies for Low Power
2.7.1 Hi-K Gate Dielectric
2.7.2 Lightly Doped Drain–Source
2.7.3 Silicon on Insulator
2.7.4 Advantages of SOI
2.7.5 FinFET

3. MOS Transistors 6 hours
3.1 Introduction
3.2 The Structure of MOS Transistors
3.3 The Fluid Model
3.3.1 The MOS Capacitor
3.3.2 The MOS Transistor
3.4 Modes of Operation of MOS Transistors
3.5 Electrical Characteristics of MOS Transistors
3.5.1 Threshold Voltage
3.5.2 Transistor Transconductance
3.5.3 Figure of Merit
3.5.4 Body Effect
3.5.5 Channel-Length Modulation
3.6 MOS Transistors as a Switch
3.6.1 Transmission Gate

4. MODELING OF MOS TRANSISTORS USING SPICE 1 hour
4.1 Basic Concepts
4.2 The LEVEL 1 Model Equations
4.3 The LEVEL 2 Model Equations
4.4 The LEVEL 3 Model Equations
4.5 Capacitance Models
4.6 Comparison of the SPICE MOSFET Models


5. MOS Inverters 6 hours
5.1 Introduction
5.2 Inverter and Its Characteristics
5.3 MOS Inverter Configurations
5.3.1 Passive Resistive as Pull-up Device
5.3.2 nMOS Depletion-Mode Transistor as Pull up
5.3.3 nMOS Enhancement-Mode Transistor as Pull up
5.3.4 The pMOS Transistor as Pull Up
5.3.5 pMOS Transistor as a Pull Up in Complementary Mode
5.3.6 Comparison of the Inverters
5.4 Inverter Ratio in Different Situations
5.4.1 An nMOS Inverter Driven by Another Inverter
5.4.2 An nMOS Inverter Driven Through Pass Transistors
5.5 Switching Characteristics
5.5.1 Delay-Time Estimation
5.5.2 Ring Oscillator
5.6 Delay Parameters
5.6.1 Resistance Estimation
5.6.2 Area Capacitance of Different Layers
5.6.3 Standard Unit of Capacitance Cg
5.6.4 The Delay Unit
5.7 Driving Large Capacitive Loads
5.7.1 Super Buffers
5.7.2 BiCMOS Inverters
5.7.3 Buffer Sizing

6. MOS Combinational Circuits 6 hours
6.1 Introduction
6.2 Pass-Transistor Logic
6.2.1 Realizing Pass-Transistor Logic
6.2.2 Advantages and Disadvantages
6.2.3 Pass-Transistor Logic Families
6.3 Gate Logic
6.3.1 Fan-In and Fan-Out
6.3.2 nMOS NAND and NOR Gates
6.3.3 CMOS Realization
6.3.4 Switching Characteristics
6.3.5 CMOS NOR Gate
6.3.6 CMOS Complex Logic Gates
6.4 MOS Dynamic Circuits
6.4.1 Single-Phase Dynamic Circuits
6.4.2 Two-Phase Dynamic Circuits
6.4.3 CMOS Dynamic Circuits
6.4.4 Advantages and Disadvantages
6.4.5 Domino CMOS Circuits
6.4.6 NORA Logic

7. SEQUENTIAL MOS LOGIC CIRCUITS 1 hour
7.1 Introduction
7.2 Behavior of Bistable Elements
7.3 The SR Latch Circuit
7.4 Clocked Latch and Flip-Flop Circuits
7.5 CMOS D-Latch and Edge-Triggered Flip-Flop

8. SEMICONDUCTOR MEMORIES 1 hour
8.1 Introduction
8.2 Read-Only Memory (ROM) Circuits
8.3 Static Read-Write Memory (SRAM) Circuits
8.4 Dynamic Read-Write Memory (DRAM) Circuits


9. LOW-POWER CMOS LOGIC CIRCUITS 3 hours
9.1 Introduction
9.2 Overview of Power Consumption
9.3 Low-Power Design Through Voltage Scaling
9.4 Estimation and Optimization of Switching Activity
9.5 Reduction of Switched Capacitance
9.6 Dynamic and Leakage power reduction techniques
9.7 Adiabatic Logic Circuits

10. VLSI DESIGN METHODOLOGIES 2 hours
10.1 Introduction
10.2 VLSI Design Flow
10.3 Design Hierarchy
10.4 Concepts of Regularity, Modularity and Locality
10.5 VLSI Design Styles
10.6 Design Quality
10.7 Packaging Technology
10.8 Computer-Aided Design Technology


11. DESIGN FOR MANUFACTURABILITY 2 hours
11.1 Introduction
11.2 Process Variations
11.3 Basic Concepts and Definitions
11.4 Design of Experiments and Performance Modeling
11.5 Parametric Yield Estimation
11.6 Parametric Yield Maximization
11.7 Worst-Case Analysis
11.8 Performance Variability Minimization
12. DESIGN FOR TESTABILITY 2 hours
12.1 Introduction
12.2 Fault Types and Models
12.3 Controllability and Observability
12.4 Ad Hoc Testable Design Techniques
12.5 Scan-Based Techniques
12.6 Built-In Self Test (BIST) Techniques
12.7 Current Monitoring IDDQ Test

13. Beyond CMOS 2 hours
13.1 CMOS Scaling limits and future challenges
13.2 Upcoming technologies
13.2.1 FinFET transistors
13.2.2 Carbon Nanotube transistors (CNT)
13.2.3 Spintronics
13.2.4 Photonics
13.2.5 Tunnel junction devices
13.2.6 Indium antimonide transistors
13.2.7 Graphene nanoribbons
13.2.8 Molecular electronics

Course Objectives

Course Outcomes

1. This course will be helpful to those who want to pursue a career in VLSI industry. <br />2. This course is a foundation for advanced courses like hardware security, fault tolerant systems, VLSI for Communication, embedded systems etc.

Essential Reading

Supplementary Reading