Course Details
Subject {L-T-P / C} : EC6275 : Reconfigurable System Design Laboratory { 0-0-3 / 2}
Subject Nature : Practical
Coordinator : Prof. Debiprasad Priyabrata Acharya
Syllabus
Experiments using FPGA : Design a full adder using Dataflow modeling Design a full adder using half-adder Design a half adder Design a 4-bit adder cum sub tractor using: (a) 4:1 MUX using the following: (a)dataflow (b)using when else (c) structural modeling using 2:1 MUX (d) behavioral modeling using (i)case statement (ii) if else statement (e)mixed style of modeling(use structural, behavioral, dataflow) Design a Decoder(3 : 8) and Encoder (Gray to Binary) Design a BCD to 7-Segment Decoder Interface the 2-bit adder with 7-segment display Design 4-bit Even/Odd parity checker & generator Design of Flip-Flops: Design of counters, Design of Shift-Register: (a)Serial-in serial-out (b)Serial-in parallel-out Design the following using Generic (a)Generic Decoder (b)Generic parity (c) detector Generic parity generator Design of controller for interfacing of PS2,LCD,VGA,UART,ADC and DAC with FPGA. Experiments using FPAA
Experiments using SOPC and PSoC
Course Objectives
- To learn the use of hardware description languages for designing reconfigurable systems
- To learn system design based on programmable logic devices like FPGAs
Course Outcomes
CO1: Create the knowledge of high level VLSI design coding language to carry out research and development in the area of digital IC design. <br />CO2: Model the digital designs including FSMs to Processor architectures using the knowledge of HDL Language. <br />CO3: Apply the knowledge of Reconfigurable architectures like FPGAs in designing and implementing digital ICs. <br />CO4: Apply the techniques to improve the timing analysis of digital circuits.. <br />CO5: Implement practical and state of the art of Digital VLSI design, suitable for real life and <br /> Industry applications.
Essential Reading
- J Bhasker, A Verilog Primer, Star Galaxy Publishing
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Supplementary Reading
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