Lab 1: Design of different Modeling Styles Using Verilog HDL
• Design a half adder.
• Design a full adder using half-adder (Structural and dataflow Modeling)

Lab 2: Design of different Modeling Styles Using Verilog HDL
• Design a 4:1 MUX using Dataflow modeling,
• Structural modeling using 2:1 MUX,
• Behavioral modeling and
• Mixed style of modeling(use structural, behavioral, dataflow)

Lab 3: Design of Combinational Circuits Using Verilog HDL
• Design a Decoder (3 : 8), Encoder (Gray to Binary) and BCD to 7-Seg Decoder.
• Interface the 2-bit adder with 7-segment display.
• Arithmetic Logic Unit

Lab 4: Design of Different Adder Architectures and its Comparative Evaluation.
• Ripple carry Adder
• Carry Save Adder
• Carry Look Ahead Adder and FPGA validation.

Lab 5: Design of Flip-Flops, Register, Shift Registers using Verilog HDL.
• Flip-Flops: DFF, J-K Flip Flop, T Flip Flop

Lab 6: Design of Counter using Verilog HDL.
• 4 bit up/down counter and 4-bit universal shift register (Sync and Async)
• Decade counter.
Lab7: Design an 8-bit Counter using Xilinx IP Integrator.
Lab 8: Implementation of 4-bit Counter in FPGA and debugging design using
Vivado Integrated Logic Analyzer.
Lab 9: Design a Sequential Moore and Mealy FSM and Implement using Basys3
FPGA board.
Lab 10:Design a Greatest Common Divisor Single Purpose Processor using
Verilog HDL.
Lab 11: Design an 8-bit General Purpose Processor Using HDL.
Lab 12: Design and Interfacing UART,ADC, LCD, VGA and Flash Memory with FPGA.

To learn the use of hardware description languages for designing reconfigurable systems

To learn system design based on programmable logic devices like FPGAs

CO1: To well versed with the HDL coding language to design digital ICs.
CO2: Able to model and analyze combinational and sequential circuits of digital design
using HDL.
CO3: Able to model and analyze memories and Finite state machine used in complex
digital design using HDL.
CO4: Learn the methodology to model a Processor architecture using HDL.
CO5: Learning the methodology of implementing the Digital design architectures and
peripherals in FPGA.
CO6: Implement in practice the state of the art of designing Digital ICs, suitable for real
life and industry applications.

J Bhasker, A Verilog Primer, Star Galaxy Publishing