Lab 1: Experiments on Basic Verification (Simulation)
• Design 4-bit counter in Verilog and Test bench program to simulate using Synopsys VCS and Cadence NcSim.
• Design a FSM for keyboard edge detection circuit and Test bench.

Lab 2: Experiments on FSM Design and Verification
• Design FSM and test bench programs in Verilog for: - Debouncing Circuit,
Division Circuit and Fibonacci number generation circuit.

Lab 3: Experiments on Coverage Analysis in Verification
• Perform the Code coverage analysis for above FSM’s using Cadence IMC tool (line, branch, toggle and FSM coverage)

Lab 4: Logic Design Synthesis
• Synthesize the Counter and above designed FSM’s using Synopsys Design Compiler (DC) with and without constraints.
• Record area, power and timing values and save the gate-level netlist. And also, study the structure of Standard Cell Library.

Lab 5: Gate Level Simulation
• Perform the Gate –level simulation for above synthesized code for all designs and debug. Perform coverage analysis at gate-level simulations.

Lab 6: DFT Insertion and Test Pattern Generation
• Generate the synthesized netlist for full adder circuit using Synopsys DC and generate the test patterns using Synopsys TetraMax. Simulate the test patterns in Synopsys VCS.
• Insert the scan chain for sequential circuits using DFT Compiler. Generate and simulate the test patterns.

Lab 7: Functional coverage for any one the FSM designed above using System
Verilog and Layered Test bench design.

Lab 8: Power Analysis using Synopsys Power Compiler and VCS (generating VCD)

Lab 9: Performing Basic Static Timing Analysis using Primetime.

Lab 10: Performing Basic Placement and Routing using Cadence Innovus.

To learn of basic design approaches of Application Specific Integrated Circuits

To finally come out with practical knowledge of doing tapeout.

CO1: To well versed with the ASIC design flow used in IC design using industry standard EDA tools (Synopsys and Cadence).
CO2: Learning the designing skill of Finite state machine used in complex digital design using HDL.
CO3: Able to perform verification of the designs by writing test benches and perform the coverage analysis
CO4: Preform synthesis of the design, generate the gate level netlist and report the area, timing and Power analysis.
CO5: Perform the gate level simulation, placement and routing of design using EDA Tools
CO6: Preform the hands-on practice of creating ICs with the knowledge of IC design flow and using industry standard EDA Tools.

Michael Smith, Application Specific Integrated Circuits, Addison welsely

Kishore Mishra, Advanced Chip Design, Createspace Independent Pub