Module1: Introduction to VLSI testing: Importance of testing, Challenges in VLSI testing, Levels of abstractions in VLSI testing, Functional vs. Structural approach to testing, Complexity of the testing problem, Controllability and Observability, Generating test for a single stuck at fault in combinational logic, D-algorithm, FAN and PODEM algorithms, Test optimization and fault coverage. (7 Hours)

Module2: Design for testability (DFT): Testability analysis, Scan cell design, Scan architectures, Scan design rules, Scan design flow, Special purpose scan designs Logic and fault simulation, Fault detection, Adhoc and structured approaches to DFT, Various kinds of scan design, Fault models for PLAs, Bridging and delay faults and their tests. (8 Hours)

Module3: Built-in self-test (BIST): Random test generation, Boolean difference, ATPG algorithms for combinational circuits, Sequential ATPG, Untestable faults, IDDQ testing The LFSRs and their use in random test generation and response compression (including MISRs), Design rules, Exhaustive testing, Pseudo-random testing, Pseudo-exhaustive testing, Output response analysis, Logic BIST architectures Test compression: Test stimulus compression, Test response compaction, Architectures for test compression. (8 Hours)

Module4: Boundary scan: IEEE standards for digital boundary scan, Embedded core test standards Analog and mixed signal testing, Delay testing, Physical failures, Soft errors Reliability, FPGA testing, MEMS testing, RF testing, High speed I/O testing. (6 Hours)

Module5: Verification techniques: Importance of verification, Verification plan, Verification flow, Levels of verification, Verification methods and languages, Introduction to Hardware Verification methodologies, Verifications based on simulation, analytical and formal approaches. Functional verification, Timing verification, Formal verification. Basics of equivalence checking and model checking. (9 Hours)

To provide an in-depth understanding of the testing and verification of VLSI circuits.

To provide an idea on importance of testing in fault tolerance.

CO1: Able to carry out research and development in the area of testing and verification of VLSI circuits.
CO2: Apply techniques to improve testability of VLSI circuits.
CO3: Utilize logic simulation methods, ATPG, BIST and boundary scan techniques in testing of VLSI circuits.
CO4: Apply functional, timing and formal verification methods at various design abstractions of VLSI circuits.
CO5: Solve practical and state of the art testing and verification problems to serve VLSI industries

Parag K. Lala, An Introduction to Logic Circuit Testing, Morgan & Claypool Publishers

Thomas Kropf, Introduction to Formal Hardware Verification, Springer

Michael L. Bushnell and Vishwani D. Agrawal, Essentials of Electronic Testing, Springer India

M. Abramovici, M. Breuer, and A. Friedman, Digital System Testing and Testable Design, Jaico Publishing House