Course Details
Subject {L-T-P / C} : EC6271 : VLSI Design Laboratory { 0-0-3 / 2}
Subject Nature : Practical
Coordinator : Prof. Ayas Kanta Swain
Syllabus
Drawing schematic of PMOS & NMOS using S-Edit and Study their Characteristics, Layout of Basic circuit elements NMOS, PMOS using L-Edit, Layout & Circuit Simulation of CMOS Inverter, Impact of supply voltage and temperature, Simulation and layout of basic gates, Simulation and layout of basic gates, Simulation and layout of Flip-Flop, Simulation and layout of memories Back-End ASIC design flow using Cadence design tools. Lay out vs Schematic (LVS).
Course Objectives
- To learn the circuit design and simulation of basic CMOS gates, flip flops and memories. <br />Layout design, DRC and LVS checks of the mentioned circuits.
- To creae the basic knowledge of designing of VLSI circuits using SPICE, schematics and layout editors.
Course Outcomes
CO1: To well versed with the back-end design flow of IC design using industry standard EDA tools (Tanner Tools). <br />CO2: Learning the skill of designing schematics and layout of basic NMOS and PMOS transistors and analyze its characteristics. <br />CO3: To create the expertise in Tanner tools, observe the temperature, voltage variation and find out the delays of circuit. <br />CO4: To draw the schematic and layout of combinational design using CMOS, dynamic logic style and perform the dc and transient analysis. <br />CO4: To draw the schematic and layout of sequential design (Flip Flop) and Memory cell (SRAM) and perform the transient analysis. <br />CO5: To perform the parasitic extraction, Layout vs Schematic analysis and power calculation of the circuits.
Essential Reading
- Sung-Mo (Steve) Kang , Yusuf Leblebici, CMOS DIGITAL INTEGRATED CIRCUITS ANALYSIS & DESIGN, McGrawHill
- , ,
Supplementary Reading
- J. M. Rabaey, A . Chandrakasan, Digital Integrated Circuits, Pearson
- , ,