Course Details
Subject {L-T-P / C} : EC4715 : VLSI Design Laboratory { 0-0-3 / 2}
Subject Nature : Practical
Coordinator : Prof. Ayas Kanta Swain
Syllabus
Use Xilinx Vivado 2018 Simulator for simulation, XST for Synthesis, and Verilog HDL.
Tanner Tool EDA - SEDIT,LEDIT and LVS
Lab 1: Study of Different Modeling Styles
1. Design a half-adder.
2. Design a full adder using a half-adder (Structural Modeling)
3. Design a full adder using Dataflow modeling.
Lab 2: Study of Different Modeling Styles
4. Design a 4:1 MUX using the following:
(a) dataflow
(b) using when else
(c) structural modeling using 2:1 MUX
(d) behavioral modeling using
i) case statement
ii) if else statement
(e) mixed style of modeling(use structural, behavioral, dataflow)
Lab 3: Study of Combinational Circuits
5. Design a Decoder(3 : 8) and Encoder (Gray to Binary)
6. Design a BCD to 7-Segment Decoder.
Lab 4: Study of Combinational Circuits
7. Interface the 2-bit adder with the 7-segment display.
8. Write Verilog HDL Code for an ALU.
Lab 5: Simulation & Comparison of Different Adder Architecture.
9. Ripple Carry Adder
10. Carry Save Adder
11. Carry Look Ahead Adder
Downloading the bit stream file in XILINX Basys3 FPGA.
Lab 6: Study of Flip-Flops and Register.
12. Design of Flip-Flops:
(a) J-K Flip Flop, T Flip Flop
(b) Serial-in parallel-out.
Lab 7: Study of Flip-Flops and Register.
13. Design of counters and use of IP-Cores
(a) 4 bit up counter(use asynchronous reset)
(b) 4-bit up/down counter
(c) Decade counter
(d) Design a counter using Xilinx IP-Core
Lab 8: Implementing Counter in FPGA.
15. Design a 4-bit up-down counter with load and select input for loading data and selecting up-down counting using Xilinx Basys3 FPGA.
Lab 9: FSMs using Verilog HDL
14. Implementation of Moore and Mealy FSM using Verilog HDL.
Lab 10: Design of an inverter using Tanner SEDIT, LEDIT, and LVS and
draw the Voltage transfer Characteristic.
Lab 11: Design of a 2-input NAND gate using Tanner SEDIT, LEDIT and
LVS. Draw the Voltage transfer Characteristic and perform transient
analysis.
Course Objectives
- To study and design digital circuits using Verilog HDL
- To implement digital design in FPGA
- To learn the design of VLSI circuits using SPICE.
- To perform schematic, layout, DRC, and LVS of the mentioned circuits.
Course Outcomes
CO1: Knowledge of designing various combinational designs using Verilog HDL <br />CO2: Knowledge of designing various sequential designs using Verilog HDL <br />CO3: Knowledge of digital design implementation in FPGA <br />CO4: Knowledge of the design of VLSI circuits using the schematic editor and simulation of circuits using SPICE <br />CO5:Knowledge of the design of VLSI circuits using layout editor, simulation of circuits using SPICE, and performing <br /> power analysis.
Essential Reading
- J Bhasker, A verilog HDL Primer, BS Publication
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Supplementary Reading
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