Course Details
Subject {L-T-P / C} : EC4715 : VLSI Design Laboratory { 0-0-3 / 2}
Subject Nature : Practical
Coordinator : Ayas Kanta Swain
Syllabus
Module 1 : |
Use Xilinx Vivado 2018 Simulator for simulation, XST for Synthesis, and Verilog HDL.
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Course Objective
1 . |
To study and design digital circuits using Verilog HDL |
2 . |
To implement digital design in FPGA |
3 . |
To learn the design of VLSI circuits using SPICE. |
4 . |
To perform schematic, layout, DRC, and LVS of the mentioned circuits. |
Course Outcome
1 . |
CO1: Knowledge of designing various combinational designs using Verilog HDL
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Essential Reading
1 . |
J Bhasker, A verilog HDL Primer, BS Publication |