S. Khandagale and S. Sarkar,"A 6-Bit 500 MSPS Segmented Current Steering DAC with On-Chip High Precision Current Reference", in IEEE International Conference on Computing, Communication and Automation (ICCCA2016), IEEE, Noida, India, April 2016, 10.1109/CCAA.2016.7813858       Inproceedings

S. Khandagale and S. Sarkar,"An 8-Bit 500 MSPS Segmented Current Steering DAC Using Chinese Abacus Technique,", in 20th International Symposium on VLSI Design and Test (VDAT), IEEE, Guwahati, India, May 2016, 10.1109/ISVDAT.2016.8064903       Inproceedings

S. Sarkar and S. Banerjee,"A 10-bit 500 MSPS segmented DAC with distributed octal biasing scheme", in 2015 International Conference on Signal Processing, Computing and Control (ISPCC), pp.145-148, IEEE, Waknaghat, India, September 2015, 10.1109/ISPCC.2015.7375014       Inproceedings

S. Sarkar and S. Banerjee,"A 10-Bit 500 MSPS segmented DAC with optimized current sources to avoid mismatch effect", in IEEE Computer Society Annual Symposium on VLSI (ISVLSI15), vol.07-10-july-2015, pp.172-177, IEEE Computer Society 2015, 10.1109/ISVLSI.2015.87       Inproceedings

S. Sarkar and S. Banerjee,"A 10 bit 1 GSPS nyquist DAC in 180 nm CMOS with high FOM", Analog Integrated Circuits and Signal Processing, vol.80, no.1, pp.59-68, Springer, July 2014, 10.1007/s10470-014-0309-x       Article

S. Sarkar and S. Banerjee,"An 8-bit low power DAC with re-used distributed binary cells architecture for reconfigurable transmitters", Microelectronics Journal, vol.45, no.6, pp.666-677, Elsevier, June 2014, 10.1016/j.mejo.2014.03.014       Article

S. Sarkar,"500 MHz differential latched current comparator for calibration of current steering DAC", in Proceedings of the 2014 IEEE Students' Technology Symposium, pp.309-312, IEEE, May 2014, 10.1109/techsym.2014.6808066       Inproceedings

S. Sarkar and S. Banerjee,"An 8-bit 1.8V 500 MSPS CMOS Segmented Current Steering DAC", in P2009 IEEE Computer Society Annual Symposium on VLSI, IEEE, May 2009, 10.1109/ISVLSI.2009.12       Inproceedings

S. Sarkar, R. S. Prasad, S. K. Dey, V. Belde, and S. Banerjee,"An 8-bit 1.8 V 500 MS/s CMOS DAC with a novel four-stage current steering architecture", in 2008 IEEE International Symposium on Circuits and Systems, pp.149-152, IEEE 2008, 10.1109/iscas.2008.4541376       Inproceedings

S. Sarkar,"Novel and simple, supply voltage and temperature compensated current reference", in Conference on Advances in Space Science and Technology (CASST), KCSTC, IIT Kharagpur, January 2008       Inproceedings