All Publications

D. Kumaradasan, S. K. Kar, and S. Sarkar,"A low-power 10-bit SAR ADC with an integrated CDAC and C-MOSCAP DAC for implantable pacemakers", in 2024 28th International Symposium on VLSI Design and Test (VDAT), pp.1-6, IEEE, September 2024, 10.1109/VDAT63601.2024.10705705       Inproceedings

M. and S. Sarkar,"A 13-bit resolution high performance time domain comparator using intermediate buffer based VCO", in TENCON 2024 - 2024 IEEE Region 10 Conference (TENCON), pp.1545-1548, IEEE, December 2024, 10.1109/TENCON61640.2024.10902767       Inproceedings

K. A. Ahmed, J. H. Te, S. Sarkar, and M. Alioto,"Dual-Mode conversion gating, comparator merging and reference-less calibration for 2.7X Energy reduction in SAR ADCs under low-activity inputs", IEEE Solid-State Circuits Letters, vol.6, IEEE 2023, 10.1109/LSSC.2023.3246063       Article

S. Samanta and S. Sarkar,"A 10-bit CS-DAC using Fully Random Rotation based DEM and Code Independent Output Impedance Compensation", AEU – International Journal of Electronics and Communications, vol.161, pp.154528, AEU 2023, https://doi.org/10.1016/j.aeue.2023.154528       Article

S. Samanta and S. Sarkar,"Mismatch Error Compensation of Hybrid CS-DAC to Achieve High Figure of Merit Utilizing On-Chip Self-Healing Assisted Swap-Enabled Randomization Technique", International Journal of Circuit Theory and Applications, vol.52, no.5, pp.2191-2204, Wiley Publications 2023, View Details       Article

S. Samanta and S. Sarkar,"A Pairwise Swap Enabled Randomized DEMAddressing Intersegment Mismatch for Current Steering Digital-to-Analog Converters", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.30, no.9, pp.1332 - 1340, IEEE 2022, 10.1109/TVLSI.2022.3183353       Article

S. Samanta and S. Sarkar,"An On-Chip Partial Self-Healing Calibration Technique for 10-bit Reused Distributed Current Steering DAC", Analog Integrated Circuits and Signal Processing, vol.113, pp.353-360, Springer 2022, 10.1007/s10470-022-02096-x       Article

S. Samanta and S. Sarkar,"Dynamic switching compensation technique mitigating code-dependent switching distortion in CS-DACs", in 2022 IEEE 19th India Council International Conference (INDICON), pp.1-5, IEEE, Kochi, India, November 2022, 10.1109/INDICON56171.2022.10039778       Inproceedings

S. Samanta and S. Sarkar,"A 10-bit 500 MSPS Segmented CS-DAC of > 77 dB SFDR upto the Nyquist with Hexa-decal biasing", in 24th International Symposium on VLSI Design and Test (VDAT) 2020, IEEE, July 2020       Inproceedings

S. Samanta and S. Sarkar,"A 1.8 V 8-bit 500 MSPS Segmented Current Steering DAC with > 66 dB SFDR", in Computer Society Annual Symposium on VLSI (ISVLSI 2020), IEEE, July 2020       Inproceedings