All Publications

S. Sarkar and S. Banerjee,"An 8-bit low power DAC with re-used distributed binary cells architecture for reconfigurable transmitters", Microelectronics Journal, vol.45, no.6, pp.666-677, Elsevier, June 2014, 10.1016/j.mejo.2014.03.014       Article

S. Sarkar,"500 MHz differential latched current comparator for calibration of current steering DAC", in Proceedings of the 2014 IEEE Students' Technology Symposium, pp.309-312, IEEE, May 2014, 10.1109/techsym.2014.6808066       Inproceedings

S. Sarkar and S. Banerjee,"An 8-bit 1.8V 500 MSPS CMOS Segmented Current Steering DAC", in P2009 IEEE Computer Society Annual Symposium on VLSI, IEEE, May 2009, 10.1109/ISVLSI.2009.12       Inproceedings

S. Sarkar, R. S. Prasad, S. K. Dey, V. Belde, and S. Banerjee,"An 8-bit 1.8 V 500 MS/s CMOS DAC with a novel four-stage current steering architecture", in 2008 IEEE International Symposium on Circuits and Systems, pp.149-152, IEEE 2008, 10.1109/iscas.2008.4541376       Inproceedings

S. Sarkar,"Novel and simple, supply voltage and temperature compensated current reference", in Conference on Advances in Space Science and Technology (CASST), KCSTC, IIT Kharagpur, January 2008       Inproceedings