All Publications

D. Kumaradasan, S. Sarkar, and S. K. Kar,"An 8-bit 1 MS/s low-power SAR ADC realized with an enhanced EPC and a randomized DEM 8× 8 CDAC", Analog Integrated Circuits and Signal Processing, vol.126, no.41, Springer Nature, February 2026, 10.1007/s10470-026-02571-9       Article

S. Samanta and S. Sarkar,"Performance enhanced current-steering DAC using distributed dual randomization dynamic element matching technique", AEU - International Journal of Electronics and Communications, vol.207, Elsevier 2026, 10.1016/j.aeue.2026.156242       Article

D. Kumaradasan, S. K. Kar, and S. Sarkar,"A low-power 10-bit SAR ADC with splitting decoder for implantable pacemakers", in 2025 IEEE 6th India Council International Subsections Conference (INDISCON), IEEE, Rourkela, India, December 2025, 10.1109/INDISCON66021.2025.11251998       Inproceedings

S. Sarkar, M., and A. Mishra,"Low power ALU design using pre-computational LUT for RV32M processor", in 2025 IEEE 6th India Council International Subsections Conference (INDISCON), pp.1-4, IEEE, Rourkela, India 2025, 10.1109/INDISCON66021.2025.11253853       Inproceedings

F. Hussain and S. Sarkar,"Comparative study of the design and analysis of ripple carry adder using reversible logic gates", Recent Trends in Intelligent Systems and Next Generation Wireless Communication, ch.31, pp.59-67, Springer, Reversible Logic, August 2025, 10.1007/978-981-96-4741-5_6       Inbook

D. Kumaradasan, S. Sarkar, and S. K. Kar,"Design and development of power-efficient SAR ADC with Dual-Path switching and triple-tail comparator for biomedical signal processing", Recent Trends in Intelligent Systems and Next Generation Wireless Communication, ch.6, pp.357-366, Springer, SAR ADC 2025, 10.1007/978-981-96-4741-5_6       Inbook

S. Samanta and S. Sarkar,"Mismatch error compensation of hybrid CS-DAC to achieve high figure of merit utilizing on-chip self-healing assisted swap-enabled randomization technique", International Journal of Circuit Theory and Applications, vol.52, no.5, pp.2191-2204, Wiley, May 2024, 10.1002/cta.3875       Article

D. Kumaradasan and S. Sarkar,"A low-power 10-bit SAR ADC with an integrated CDAC and C-MOSCAP DAC for implantable pacemakers", in 28th International Symposium on VLSI Design and Test (VDAT-2024), IEEE VDAT 24 2024       Inproceedings

D. Kumaradasan, S. K. Kar, and S. Sarkar,"An 8-bit 100 kS/s Low Power SAR ADC with Modified EPC for Bio-Medical Applications", in 2023 IEEE Silchar Subsection Conference (SILCON), pp.1-6, IEEE, January 2024, 10.1109/SILCON59133.2023.10404914       Inproceedings

I. Dash, S. K. Kar, and S. Sarkar,"Noise analysis in switched capacitor-based differential capacitive interfacing circuits", in 2024 IEEE 21st India Council International Conference (INDICON), IEEE 2024, 10.1109/INDICON63790.2024.10958540       Inproceedings