RISC-V is drawing new interest from both the academic and corporate worlds, and that interest promises to yield a growing number of open-source implementations of the ISA. Compared to some other ISAs, the instruction set of RISC-V seems particularly well-suited for scalability. Not only can it be efficiently implemented in simple processors, but it can also serve as the foundation for both increasingly large designs and increasingly complex designs. The cores that have been developed thus far based on the RISC-V ISA vary tremendously in their scale and capability, not to mention the virtually unlimited design space for potential future RISC-V cores. DSP applications need special hardware features from their processors. These are for efficient multiplication and operations with complex numbers. Multiplication is the critical operation that consumes the most time, power, and area. So, for example, using two multipliers instead of four in a complex multiplication operation helps optimize performance. Among architectures for multipliers, the radix-4 Booth multiplier has exceptional speed and lower power consumption. For addition and subtraction, the adder preferred is the Brent-Kung adder. The Kogge-Stone adder could be chosen for higher performance and at the expense of what would seem optimally power and area consumption. But the Berg-Kung adder has a lower power and area profile, and one pays a slight performance cost for that advantage. One innovative method to speed up arithmetic circuits is the use of redundant number systems (RNS). By eliminating the need for conversions between RNS and binary formats, which can slow down processing, RNS can enhance performance. Applying RNS throughout the entire processor data path, instead of just in certain subcircuits, can yield substantial performance gains. RISC-V is particularly well-suited for RNS due to its lack of a flags register, which lowers computational costs when utilizing RNS. Artificial intelligence (AI) is playing an increasingly significant role in technological advancements, with techniques such as deep neural networks (DNN), convolutional neural networks (CNN), and graph convolutional networks (GCN) becoming more common. However, these AI models often demand extensive computing and storage resources, which can hinder their performance. Recent studies have aimed at tailoring the RISC-V instruction set architecture (ISA) to enhance AI capabilities. One notable development is the posit processing unit (PPU), designed to speed up DNN weight compression using the posit format. This innovation facilitates efficient conversion between 8 or 16-bit posits and 32-bit IEEE floating-point or fixed-point formats, while maintaining minimal precision loss. By incorporating a PPU into a RISC-V core alongside the floating-point unit (FPU) and arithmetic logic unit (ALU), DNN inference can be significantly accelerated, cutting inference time by a factor of 10.