Syllabus

Task-I: Introduction / Practice Session [3 hr.]
Realize the AND & OR gate by using dataflow and behavioural modelling using VHDL and Verilog HDL.

Task-II: Realization of Digital circuits using VHDL/Verilog HDL [6 hr.]
1. 4:1 MUX by using 2:1 MUX in structural modelling.
2. JK Flip-flop
3. Multiplier
4. Adder
Task-III: Realization of Counter using VHDL /Verilog HDL [6 hr.]

Task-IV: Finite State Machine for Sequence Detection [6 hr.]

Task-V: ADC-DAC Interface with FPGA/SoC using I2C & SPI protocol [6 hr.]

Task-VI: FIR & IIR Digital Filter Structure Realization on FPGA/SoC [6 hr.]

Learn to use modern circuit design tools, software, and equipment to develop digital circuit in embedded systems

Learn coding in VHDL/Verilog, simulation and testing

Learn to design and implement embedded system with optimal computational complexity

After completing the course the students will be able to:
CO1: Design and implement basic logic gates (AND, OR) using dataflow and behavioral modeling techniques in VHDL
and Verilog HDL.
CO2: Design and realize digital circuits, such as 4:1 MUX using 2:1 MUX in structural modeling, JK Flip-flop, multiplier,
and adder using VHDL/Verilog HDL.
CO3: Implement and simulate sequential and combinational circuits, including counters, Finite State Machine (FSM) using
VHDL/Verilog HDL..
CO4: Understand and implement ADC-DAC interfacing using I2C & SPI protocol techniques with FPGA/SoC platforms
for signal conversion applications.
CO5: Design and implement digital filter structures using FPGA/SoC for signal processing applications.

Douglas L. Perry, VHDL: Programming by Example, Tata McGraw-Hill , 4th Ed., 2002

D. M. Harris and S. L. Harris, Digital Design and Computer Architecture, Morgan Kaufmann , Latest Ed. or 2007

Anonymous, Data Sheets of Various components, manufacturers , latest

M. Morris Mano, Computer System Architecture, PHI , 3rd Ed., 2007