Syllabus

Module-1: Definition of Technology node, Basic CMOS Process flow, MOS Scaling theory, Issues in scaling MOS transistors: Short channel effects, Description of a typical 65 nm CMOS technology, Requirements for Non classical MOS transistor, MOS capacitor, Role of interface quality and related process techniques, Gate oxide thickness scaling trend, SiO2 vs High-k gate dielectrics, Integration issues of high-k, Interface states, bulk charge.

Module-2: Metal gate transistor: Motivation, Transport in Nano MOSFET, velocity saturation, ballistic transport, injection velocity, velocity overshoot.

Module-3: SOI - PDSOI and FDSOI. Ultrathin body SOI - double gate transistors, integration issues, Vertical transistors - FinFET and Surround gate FET.

Module-4: Metal source/drain junctions - Properties of schotky junctions on Silicon, Germanium and compound semiconductors.

Module-5: Synthesis of Nanomaterials: CVD, Nucleation and Growth, ALD, Epitaxy, MBE, Compound semiconductor hetero-structure growth and characterization: Quantum wells.

To make students aware of microelectronic circuits and their fabrication processes along with the latest technology and their modern applications.

To understand evolution of FET with technology Scaling.

CO1: Explore the issues with short channel devices.
CO2: Learn about the evolution of FET gate over channel.
CO3: Understand the SOI FET technology.
CO4: Understand the problem in metal semiconductor contact formation.
CO5: Able to define the various process steps for Nano device fabrication.

Y. Taur and T. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press

Plummer, Deal , Griffin, Silicon VLSI Technology, Pearson Education

Brundle, C.Richard Evans, Charles A. Jr. Wilson, Shaun, Encyclopedia of Materials Characterization, Elsevier.

S. M. Szee, Semiconductor Devices: Physics and technology, WILEy

IEEE Transaction of Solid State Circuits